1. Field
This disclosure relates generally to non-volatile memories (NVMs), and more specifically, to conditions for performing a read of memory cells of an NVM.
2. Related Art
An NVM typically has millions of memory transistors that are in a programmed or erased state. A transistor is programmed or erased by adjusting the threshold of the transistor through some form of tunneling of charges into the gate oxide so that if the gate and source of the transistor are biased to a pre-determined voltage and a pre-determined current is impressed on the drain of the transistor as shown in FIG. 1, the drain current of the transistor will be a measure of the programmed or erased state of the transistor.
The difference between the program and erase voltages for the transistors in the array will be dependent on process variations, variations in the voltages used to force charge tunneling, temperature, program/erase disturb, trap up, and the number of times the transistor has been erased and programmed. In general if all transistors are erased and the drain voltages are measured the result will be a roughly Gaussian distribution as shown in FIG. 2. For some NVM's the mean of the distribution will be a low voltage and the highest voltage in the distribution is called the “least erased level” (LEL). For those NVM's the mean of the distribution of programmed transistors will be a higher voltage and the lowest voltage in the distribution is called the “least programmed level” (LPL) as shown in FIG. 3. After a transistor is programmed or erased the drain voltage is checked to insure the drain voltage is less than the LEL or greater than the LPL. Verification voltages, called the “Erase Verify” (EV) and “Program Verify” (PV) voltages are selected to insure that a transistor is successfully programmed or erased. The EV is slightly greater than the LEL and the PV is slightly less than the LPL.
During normal operation, to determine if the transistor is programmed or erased, the drain voltage is compared to a pre-determined READ voltage by a sense amplifier. The READ voltage is generally a value greater than the LEL voltage and less than the LPL voltage. The selection of the READ voltage can be difficult because the difference between the LEL and the LPL may not be large and cannot be determined a priori. In addition, the LEL and LPL will shift during the life of the NVM. Finally, other design constraints such as sense amplifier resolution will constrict the usable window between the LEL and LPL. Selection of the READ, PV, and EV voltages requires a great deal of effort. Typically a large number of NVM arrays from a large number of wafers are operated and tested for a considerable time in an effort to predict the lifetime performance of the NVM. FIG. 5 shows the variation in the erase and program distributions that are caused by processing variation, aging and cycling. This is an expensive undertaking and greatly extends the development time of NVM technology.
Accordingly, it is desirable to improve upon the issues raised above concerning reading an NVM memory.